The invention is in the field of nonvolatile trench memories, and relates specifically to memory devices such as Electrically Erasable and Programmable Read Only Memory (EEPROM) Devices and methods for making such devices.
EEPROM devices in general, and methods for making such devices, are well known in the art. Some typical prior-art memory devices and methods are shown and discussed in Japanese Kokai Nos. 1-227477, 1-20668, 62-269363, 61-256673 and 3-1574. Additional background concerning memory cell configurations and technology is provided in "A 0.5.mu. BiCMOS Technology for Logic and 4Mbit-class SRAM's", R. Eklund, et al, IEDM89-425 and "A 3.6.mu..sup.2 Memory Cell Structure for 16MB EPROMS", Y. S. Hisamune, et al, IEDM89-583. Finally, an EEPROM device with a trench structure similar to that of the present invention is shown in U.S. patent application Ser. No. 610,598 now U.S. Pat. No. 5,146,426, of Mukherjee et al, filed Nov. 8, 1990, and incorporated herein by reference. As discussed in the last-mentioned reference, one of the ongoing goals of memory device technology is to create device designs and fabrication techniques which will result in simple, compact and easy-to-manufacture devices.
In the past, using conventional lithographic techniques, alignment tolerances and drain contact metallization have limited both the degree of simplification and the degree of size reduction that could be obtained. Japanese Kokai No. 1-20668, for example, is directed to improved density and size reduction in PROM devices. Nevertheless, in that reference, a complex structure is employed in which the word line clearly overlaps the trench, and in which the drain contact metallization must be laterally isolated from surrounding parts of the device by separate insulation regions. Both of these features increase the size and complexity of the resulting device.
Using prior-art techniques, the smallest known EEPROM cell has a cell area of 3.6 microns.sup.2. Although the trench memory cell configuration lends itself to further size reduction because the channel can be stretched in the vertical direction to avoid operational problems without increasing device area, the potential advantages of this device configuration have not heretofore been fully realized due to conventional lithography alignment tolerances and space-consuming drain-contact metallization configurations.